Introspection | USearch for Rust

let description = index.describe()?;
println!("{} entries in {} bytes", description.size, description.memory_usage);
println!("dispatched to {} and {}", description.cpu_class, description.gpu_class);
println!("compiled for {}", usearch::capabilities_compiled());
println!("available here {}", usearch::capabilities_available());

let reachability = index.health()?;
println!("{} of {} entries reachable", reachability.reachable, reachability.audited);

println!("{} entries under {key}, contained: {}", index.count(key)?, index.contains(key)?);

describe reads the frozen metadata and the counters once each, so under concurrent insertions they may come from slightly different moments, and memory_usage excludes the executor’s scratch. health audits how much of the graph a search reaches from its landmarks; entries it misses stay unfound until a refine re-links them. contains is the blocking shorthand for a nonzero count.

API

StructDenseIndexDescriptionA live index's frozen metadata and current counters, each read once, so under concurrent insertions they may come from slightly different moments.

dense_index.rs:683 ↗

pub struct DenseIndexDescription

Fields

`metadata`	`DenseMetadata`	The frozen metric, quantization, dimensions and connectivity, as a checkpoint reports them.
`size`	`usize`	Stored entries.
`capacity`	`usize`	Entries hosted without growing again.
`memory_usage`	`usize`	Bytes the handle holds; traversal scratch is the executor's.
`cpu_class`	`&'static str`	The CPU class dispatch picked on this machine, as `CPUClass` spells it.
`gpu_class`	`&'static str`	The GPU class dispatch picked on the index's devices; "unknown" for a host index.
`shards_count`	`usize`	Live shards.

Implements

Clone, Copy, StructuralPartialEq, PartialEq, Eq, Debug, Hash

StructDenseReachabilityOne reachability audit: the population it judged, and how much of it a search reaches.

dense_index.rs:723 ↗

pub struct DenseReachability

Fields

`audited`	`usize`	Entries published when the audit started; compare `reachable` against this, never a later size.
`reachable`	`usize`	Of those, the entries a search reaches; the rest no search finds until a refinement re-links them.
`sweeps`	`usize`	Levels the sweep took to converge; the deepest shard's on a sharded handle.
`back_sweeps`	`usize`	Levels the sweep back toward the entry point took, where an audit sweeps both ways.

Implements

Clone, Copy, StructuralPartialEq, PartialEq, Eq, Debug, Default

EnumCPUClassThe CPU families USearch ships tuned variants for: dispatch reports its pick in this vocabulary, and a RAM or NVMe placement or executor may pin one.

types.rs:1348 ↗

pub enum CPUClass

Values

`Serial`	`1`	The portable floor: no SIMD assumptions.
`IntelHaswell`	`2`	Haswell-class x86: AVX2 & FMA, the 256-bit floor.
`IntelSierra`	`3`	Sierra Forest-class x86 - the E-core Xeons: AVX-VNNI and its successors without AVX-512.
`IntelSkylake`	`4`	Skylake-class x86: the AVX-512 foundation tier.
`IntelIcelake`	`5`	Icelake-class x86: AVX-512 VNNI & VPOPCNT.
`AmdGenoa`	`6`	Genoa-class x86 - Zen 4 and newer: native bf16 dot products over AVX-512.
`IntelSapphire`	`7`	Sapphire Rapids-class x86: the Genoa bundle plus AVX-512 FP16 and the AMX-BF16 & AMX-INT8 tiles.
`IntelGranite`	`8`	Granite Rapids-class x86: the Sapphire Rapids bundle plus the AMX-FP16 tiles.
`IntelDiamond`	`9`	Diamond Rapids-class x86: the Granite Rapids bundle plus AVX10.2's FP8 conversions.
`AwsG2`	`10`	Graviton2-class Arm - Neoverse N1, the bare NEON floor.
`AppleM2`	`11`	Armv8.6+ NEON: dot products, bf16 & f16 fused multiplies - Apple M2 class silicon.
`AppleM4`	`12`	Apple M4-class Arm: the Armv8.6 NEON bundle plus the SME outer-product tiles.
`AwsG5`	`13`	Graviton5-class Arm - Neoverse V3, Armv9.2.
`NvidiaVera`	`14`	Vera-class Arm - NVIDIA's Armv9.2-generation cores with FP8 dot products.
`AlibabaC930`	`15`	Alibaba C930-class RISC-V - T-Head's XuanTie core, RVA23 vectors.
`Wasm32V128`	`16`	WebAssembly every engine loads: 32-bit, single-threaded, the fixed-width simd128 tier.
`Wasm64Extended`	`17`	WebAssembly with relaxed SIMD, shared memory for real thread pools, and 64-bit addressing.
`Monoversioned`	`18`	The one class of a monoversioned build, with every capability its floor implies or its preset vouches for.

Implements

Clone, Copy, StructuralPartialEq, PartialEq, Eq, Debug, Hash, Display

EnumGPUClassThe GPU families USearch ships tuned variants for, the device twin of [CPUClass]: a VRAM placement or executor may pin one.

types.rs:1402 ↗

pub enum GPUClass

Values

`NvidiaAmpere`	`1`	Ampere-class NVIDIA and every GPU without a class of its own - A100, A10 & RTX 30.
`NvidiaAda`	`2`	Ada-class NVIDIA - L4, L40S & RTX 40: the fp8 conversions.
`NvidiaHopper`	`3`	Hopper-class NVIDIA - H100 & H200.
`NvidiaBlackwell`	`4`	Blackwell-class NVIDIA - B200, B300 & GB300.
`NvidiaBlackwellRtx`	`5`	Consumer Blackwell NVIDIA - RTX 50, RTX PRO 6000 & DGX Spark.
`NvidiaRubin`	`6`	Rubin-class NVIDIA - the Vera-Rubin platform's device half.
`AmdCdna3`	`7`	CDNA3 AMD - MI300X & MI325X: gfx942, FNUZ fp8.
`AmdCdna4`	`8`	CDNA4 AMD - MI350X & MI355X: gfx950, OCP fp8.
`AmdCdna5`	`9`	CDNA5 AMD - MI400: gfx1250.
`AppleMetal7`	`10`	Apple7-family GPUs and every Apple GPU without a class of its own - M1 & M2.
`AppleMetal9`	`11`	Apple9-family GPUs - M3 & M4.
`AppleMetal10`	`12`	Apple10-family GPUs - M5.

Implements

Clone, Copy, StructuralPartialEq, PartialEq, Eq, Debug, Hash, Display

Functions

versionThe version of the linked library.

lib.rs:676 ↗

pub fn version() -> &'static str

capabilities_compiledComma-separated hardware capabilities the library was compiled with.

lib.rs:679 ↗

pub fn capabilities_compiled() -> &'static str

capabilities_availableComma-separated hardware capabilities this machine offers at runtime.

lib.rs:682 ↗

pub fn capabilities_available() -> &'static str